1. Field of the Invention
The invention relates to a process for producing undercut mask profiles for use in semiconductor manufacturing and to an application of the process in the fabrication of field effect transistors where the process permits self-alignment of all three important device parts, namely the implanted contact regions, the ohmic- and the gate-metallizations, with respect to each other.
There has been a dramatic increase in the use of integrated circuits over the last decade which resulted in an increasing demand for smaller device dimensions. A number of methods are known to increase the integration density of integrated circuits. By using electron and X-ray exposure methods instead of the hitherto used light radiation, progress was made in the direction of a higher resolution. There were, furthermore, efforts to reach very narrow line widths in the range of 1 .mu.m and less by extending conventional lithographic processes thereby avoiding the cost-intensive techniques of electron and X-ray lithography. With the technique of plasma or reactive ion etching for etching metals, semiconductors and dielectric materials, further developments took place in the direction of very narrow line widths and consequently toward improved device performance.
One approach, by which sub-micron resolution can be achieved, makes use of underetching techniques to obtain undercut structures serving as masks in subsequent process steps. These undercut structures, often T-shaped, are used to define very small, sub-micron lateral device dimensions. Basically, the lateral undercut dimensions are transferred to the underlying semiconductor surface by using non-isotropic processes to project the "top" of the T-profile, and by using isotropic processes to project the "foot" of the T.
A great variety of materials and methods have been utilized or suggested for the formation of such undercut structures. Most commonly, different materials are used for the "top" and for the "foot" of the T, respectively. A material combination often described is silicon nitride (Si.sub.3 N.sub.4) - silicon dioxide (SiO.sub.2).
Multi-layer photoresist structures, the layers consisting of different resists, have also been proposed in the literature, e.g., in the article "Self-Align Implantation for n.sup.+ -Layer Technology (SAINT) for High-Speed GaAs ICs" (Electronics Letters, February 1982, Vol. 18, No. 3, pp. 119-121). A similar approach has been described in the article "GaAs/(GaAl)As Heterojunction Bipolar Transistors Using a Self-Aligned Substitutional Emitter Process" (IEEE Electron Device Letters, Vol. EDL-7, No. 1, January 1986).
These photoresist methods, however, face the drawback that the resulting undercut structures are not stable at the elevated temperatures of subsequent annealing or alloying steps in the semiconductor device fabrication process.
There have also been proposals for techniques aimed at a reduction of the number of steps needed to produce the undercut structures. In these proposals, the etch rate of a single material is varied either during deposition or it is influenced by the neighborhood of other materials. Such single-material techniques are described in the following references:
"Method of Influencing the Etch-Rate of PECVD Films and Applications of the Method" (IBM Technical Disclosure Bulletin, Vol. 24, No. 11B, April 1982, p. 6094). According to the described method, the etch-rate of PECVD films formed by hydrogen-containing compounds is decreased by ion irradiation. It is suggested that, by selective irradiation, the method can be used to form patterned films without using a mask.
"High Temperature Lift-Off Structure" (IBM Technical Disclosure Bulletin, Vol. 26, No. 12, May 1984, pp. 6506-6507). Here, a recursive lift-off profile is obtained by varying the composition of a silicon nitride layer throughout the layer thickness so that a varying etch-rate is obtained for isotropic plasma etching. The change in composition is obtained by changing the temperature during the deposition process.
"Method for Characterizing the Si.sub.3 N.sub.4 Dry Etch Process" (IBM Technical Disclosure Bulletin, Vol. 21, No. 9, February 1979, p. 3654). The described method is based on the discovery that the etch-rate of SiO.sub.2 is increased in the immediate vicinity of an applied top Si.sub.3 N.sub.4 layer whereas the etch-rate in the more distant SiO.sub.2 remains unaffected. An etch-rate ratio of 3 is reported.
U.S. Pat. No. 3,639,186 discloses a process for the fabrication of high resolution pattern. An undercut is obtained in a SiO.sub.2 layer by using the effect that the etch-rate of the SiO.sub.2 is increased in the vicinity of Si which could, as in the described example, be the substrate material on which the pattern is to be formed.
Although these single-material methods require fewer process steps than required for multi-material mask profiles, there are concerns since the processes require complex tools (with selective ion irradiation), are time consuming (when the temperature is changed) or cause severe restrictions as to the materials that can be used (when relying on "neighborhood" effects).
The above cited references are representative of the present state of the art in undercut structure techniques. They disclose a wide variety of processes for forming undercut profiles but they do not disclose or suggest the basic concept underlying the present invention, i.e., the use of different plasma excitation frequencies to obtain different etch-rates.
This novel process for forming undercut structures is a prerequisite for the new method of the fabricating fully self-aligned Field Effect Transistor (FET) structures also described herein.
A variety of FET structures and processes for their fabrication have already been proposed, among others there are those for metal-semiconductor field effect transistors (MESFET) using GaAs. Basically, there are two types of processes for the fabrication of self-aligned GaAs MESFETs: one type of process uses a refractory gate metal as mask for the implantation of the ohmic contact regions, the other type of process uses a "dummy" gate as mask for the contact implant, the dummy gate being replaced by a Schottky gate after ohmic contact metal deposition and alloying.
Refractory gate structures and processes have the advantage of process simplicity. They allow the fabrication of a simple FET structure with a relatively small number of lithographic steps. The prime concern with this process however is the stability of the metal-semiconductor interface on annealing. Since the gate deposition takes place prior to the ohmic contact region implant, the Schottky barrier at the gate-channel interface is exposed to high temperature cycles required to electrically activate the implanted material and to alloy the ohmic contacts. During these high-temperature processes the metal-semiconductor interface changes due to interdiffusion, lateral diffusion, stress, shrinkage, etc. This affects the Schottky barrier height and the threshold voltage of the transistor. Dummy gate structures and processes have been proposed by K. Yamasaki et al. in articles "GaAs LSI-Directed MESFET's with Self-Aligned Implantation for n.sup.+ -Layer Technology (SAINT)" (IEEE Trans., ED-29, No. 11 pp. 1772-1777 (Nov. 1982)) and "Self-Align Implantation for n.sup.+ -Layer Technology (SAINT) for High-Speed GaAs ICs" (Electronics Letters, Vol. 18, pp. 119-121, (1982)). The use of a dummy gate makes the fabrication process for MESFET's more complicated compared to the refractory-gate process, however, it offers a number of advantages:
The metal-semiconductor interface is not exposed to a high-temperature cycle and therefore is not distorted since the actual gate metal deposition is done after the contact region implant anneal process.
There is more freedom in the choice of the gate material. The requirements are determined by the final process steps such as chip mounting, packaging, etc., which are significantly less stringent than with the high-temperature implant anneal.
The sequence of process steps permits FET channel measurements (between ohmic contacts) and characterization prior to gate metal deposition, i.e., a final adjustment of the channel threshold can be achieved before device completion, e.g., by channel recessing, thereby improving the yield.
The gate metal can be used as the first-level wiring.
The SAINT process referred to above uses a multi-layer dummy gate mask consisting of different photoresists. The photoresist mask can serve as mask for the implantation of the n.sup.+ -contact regions but does not withstand the high temperature of the following annealing step. As a result, the gate metallization and the ohmic metallization are not self-aligned with respect to the implanted contact regions. Truly self-aligned metallizations are, however, highly desirable to keep parasitic effects, in particular n.sup.+ layer series resistances, small.
A fully self-aligned MESFET fabrication process has been described in co-pending European patent application No. 85.115572.1. In that process, a multi-layer "inverted T" profile is used as mask for the n.sup.+ -implant and for the ohmic- and gate-metallizations. The upper part of the inverted T is the dummy gate which is replaced by the Schottky gate after ohmic contact metal deposition. The source-gate and drain-gate separations are determined by the difference in width of the upper and lower parts of the inverted T.
The main concern regarding this process is its complexity, particularly the opening of the via hole for the gate definition becomes very critical for sub-micron device dimensions.
It is a main object of the present invention to extend the use of conventional lithographic processes to dimensions in the sub-micron range by utilizing underetch techniques to produce undercut mask profiles.
Another object is to provide a process for producing undercut mask profiles that are temperature stable and that can be obtained using conventional, easy-to-control process steps.
A further object is to provide a field effect transistor fabrication process which allows self-alignment of all critical device parts, namely the gate and ohmic contact metallizations and the implanted contact regions, with respect to each other.
The invention as claimed is intended to meet the above objectives and to remedy the drawbacks encountered with hitherto known processes. It provides a temperature-stable undercut mask structure obtained by underetching a nitride structure in which etch-ratio variations in the order of 1:20 are obtained by changing the plasma excitation frequency of the PECVD process that is used to grow the nitride structure. The invention also solves the complexity problem in the fabrication of fully self-aligned FET devices in that the temperature-stable mask provided by the invention substantially simplifies the mask-profile transfer onto the semiconductor surface where the FET device is to be formed.
The advantages offered by the inventive process are mainly that it requires fewer and less critical process steps. Providing the same resolution and reproducibility as obtainable with the best known processes, the new process permits a substantial reduction in process complexity, tooling needs and processing time, thus resulting in substantial cost savings.